In typical circuit design, circuit components are arranged to optimize space and/or circuit performance. Such arrangements can include the “layout” or pattern definition of each of the layers used in a semiconductor manufacturing process. For example, such layout can include metal interconnect layers that are converted to masks or reticles for use in a wafer fabrication facility that manufactures ICs (i.e., “chips”).
While some circuits are designed using “custom” layout, others are designed using a partially or fully automated design flow. Application-Specific Integrated Circuit (ASIC) designs, as well as other functional blocks within a larger chip, such as System-On-Chip (SOC) designs, may employ custom and/or ASIC type flows on the same chip. In any event, typical ASIC flows use “place-and-route” tools for placing logic or circuit “blocks” and then “routing” or connecting the interface signals between the blocks.
Referring now to FIG. 1, a box diagram of a circuit block placement resulting from the use of conventional placement tools is shown and indicated by the general reference character 100. Logic Block 102 can interface to Logic Block 104 via signal 102-S. Similarly, Logic Block 104 can interface to Logic Block 106 via signal 104-S. In this example, Logic Block 102 and Logic Block 106 are initially placed by the conventional placement tool. Then, Logic Block 104 is placed. Because of interfaces to both Logic Block 102 and Logic Block 106, the conventional placement tool will place Logic Block 104 either arbitrarily or substantially in the middle between Logic Blocks 102 and 106 (i.e., distance X is about equal to distance X′). One conventional approach, for example, uses a summation of the squares in the interface signal paths to determine the middle location for the placement of Logic Block 104.
However, such conventional approaches to automated block placement are not optimized for power consumption or signal integrity concerns. Limitations of such conventional approaches result from the fact that the switching frequency of signal 102-S is not likely to be the same as that of signal 104-S. Accordingly, the placement of Logic Block 104 substantially in the middle between Logic Blocks 102 and 106 does not necessarily minimize the power being drawn or the supply noise in the situation where the switching frequencies are not equal.
Given the increasing demands on circuit designers to create chips of increasing density, decreasing wire and transistor widths, and decreasing power supply and power consumption, it is difficult to ensure optimal circuit block placement, particularly in an automated placement flow. Increasing the complexity, flexibility and/or functionality of the circuitry on a chip exacerbates these challenges. Thus, what is needed is a tool with which integrated circuit designers can automatically optimize circuit placement so as to reduce power consumption and increase signal integrity.